Modern high-speed integrated circuit (IC) devices, such as synchronous dynamic random access memories (SDRAM), microprocessors, etc., rely upon clock signals to control the flow of commands, data, addresses, etc., into, through, and out of the devices. The improved performance of ICs and the growing trend to include several computing devices or system components on a single circuit board present a challenge with respect to synchronizing the timing of all system components.
One synchronization implementation includes a delay locked loop which is used as an internal clock signal generator. Conventional delay locked loops use an adjustable delay line comprised of a series of connectable delay elements. Digital information is used to either include or exclude a certain number of delay elements within a delay line. In a conventional delay locked loop, a clock input buffer accepts a reference clock signal and transmits the signal to one or more delay lines including delay elements. The delay of the delay path is increased from a minimum setting until the edge of a delayed clock signal is eventually time-shifted just past the next corresponding edge of the reference clock signal. As an element of a conventional delay locked loop, a digital phase detector controls the delay line propagation delay so that the delayed clock signal remains synchronized with the reference clock signal. The reference clock is then used to synchronize outgoing data bits with an incoming clock signal independent of the clock frequency.
FIG. 1 is a block diagram illustrating a conventional delay locked loop 100 including a variable delay line 102 that receives a buffered clock signal BCLK and generates a delayed clock signal DCLK in response to buffered clock signal BCLK. The variable delay line 102 controls a variable delay DD of delayed clock signal DCLK signal relative to the buffered clock signal BCLK in response to a delay adjustment signal DA. A feedback delay line 104 generates a feedback clock signal FBCLK in response to delayed clock signal DCLK, wherein feedback clock signal FBCLK has a model delay (DI+DO) relative to delayed clock signal DCLK. The DI component of the model delay (DI+DO) corresponds to a delay introduced by an input buffer 106, while the DO component of the model delay corresponds to a delay introduced by an output buffer 108. Although input buffer 106 and output buffer 108 are illustrated as single components, each represents all components and the associated delay between the input and output of the delay locked loop 100. Stated another way, input buffer 106 represents the delay DI of all components between an input that receives reference clock signal CLK and an input to the variable delay line 102. Furthermore, output buffer 108 represents the delay DO of all components between the output of the variable delay line 102 and an output at which synchronized clock signal SYNCCLK is generated. Delay lock loop 100 further includes a phase detector 110 that receives feedback clock signal FBCLK and buffered clock signal BCLK, and generates a delay control signal DCON having a value indicating a phase difference between the BCLK and FBCLK signals. A delay controller 112 generates the DA signal in response to the DCON signal from the phase detector 110, and applies the DA signal to the variable delay line 102 to adjust the variable delay DD of delayed clock signal DCLK.
In operation, phase detector 110 detects a phase difference between buffered clock signal BCLK and feedback clock signal FBCLK. Thereafter, phase detector 110 and delay controller 112 operate in combination to adjust the variable delay DD of delayed clock signal DCLK signal until the phase difference between the BCLK and FBCLK signals is approximately zero. More specifically, as the variable delay DD of delayed clock signal DCLK signal is adjusted, the phase of the feedback clock signal FBCLK from the feedback delay line 104 is adjusted accordingly until the feedback clock signal FBCLK is in phase with buffered clock signal BCLK. When the delay locked loop 100 has adjusted the variable delay DD to a value causing the phase shift between the BCLK and FBCLK signals to equal approximately zero, the delay locked loop 100 is “locked.” When the delay locked loop 100 is locked, the CLK and SYNCCLK signals are synchronized.
As clock speeds of electronic systems increase, conventional delay locked loops and, more specifically, feedback lines within conventional delay locked loops, may exhibit operational problems including increased operating current, transient noise, and duty cycle distortion. As a result, the accuracy and performance of a delay locked loop may be affected.
There is a need for methods, devices, and systems to enhance the operation of delay locked loops.